x86/amd: Add support for read-only APERF/MPERF

AMD is adding support for a read-only mode of the APERF
and MPERF MSRs. When this mode is enabled, writes to
these registers are ignored and do no reset the registers.
This allows multiple well-behaved programs to share the
use of the registers even if a poorly behaved program
attempts to reset them. Support for this feature is
indicated by a CPUID bit.

AMD has been recommending that well-behaved software
avoid resetting the APERF and MPERF MSRs. Enabling
this feature should not change the behavior of well-
behaved software. This change has been tested with the
turbostat and cpufreq-aperf applications.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 386b0c2e387428d4974c2ba2e66f73bd858cf6b0..b1af0eea7f4bbc59891bc56aaaaf61bf3c0ff967 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -499,6 +499,12 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
        if (c->x86 > 0xf && !cpu_has_amd_erratum(c, AMD_ERRATUM_400))
                set_bit(X86_FEATURE_ARAT, c->x86_capability);
 
+       if (cpuid_edx(0x80000007) & (1 << 10)) {
+               rdmsr(MSR_K7_HWCR, l, h);
+               l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
+               wrmsr(MSR_K7_HWCR, l, h);
+       }
+
        /* Prevent TSC drift in non single-processor, single-core platforms. */
        if ((smp_processor_id() == 1) && c1_ramping_may_cause_clock_drift(c))
                disable_c1_ramping();